Download e-book for kindle: Architecture of High Performance Computers: Volume I by R. N. Ibbett, N. P. Topham (auth.)

By R. N. Ibbett, N. P. Topham (auth.)

ISBN-10: 1489967125

ISBN-13: 9781489967121

ISBN-10: 1489967141

ISBN-13: 9781489967145

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Extra info for Architecture of High Performance Computers: Volume I Uniprocessors and vector processors

Example text

Access to central storage from the processors in a 3090 system is provided through a system control element. Using the store-in-cache principle, any lines in a cache that have been stored into become, in effect, part of the central storage system. Thus the latest copy of a variable may be in the processor's local cache, in central storage, or in the cache of another processor. The design of the system control element must therefore take this into account. Further discussion of the problems of cache consistency in multiprocessor systems can be found in Volume II.

5 JLS cycle-time Mass (core) Store and a Fixed-head Disc Store. Pages are brought into the Local Store from either the Mass Store or the Fixedhead Disc Store, but are rejected first to Mass and later to the Fixed-head Disc. The one-level store contains all the working space and files needed by current terminal users and active background jobs. Most of the files, however, are stored on large capacity discs attached to aseparate PDP11/10 minicomputer. 1 The Exchange In order to provide a completely general and Hexihle interconnection scheme, allowing for data transfers between all these various stores and processors, an Ezchange was developed as part of the MU5 project [LTE77 ,MI79].

For both sets of measurements it is clear that the static and dynamic code requirements are approximately the same for all three systems, while the numbers of instructions obeyed show decreases as the nurober of addresses in the instruction format increases. In terms of overall system performance, however, these differences could only be translated into significant improvements if the instruction and operand accessing rates could be improved correspondingly, since we can assume that the arithmetic speeds would be the same in each case.

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Architecture of High Performance Computers: Volume I Uniprocessors and vector processors by R. N. Ibbett, N. P. Topham (auth.)

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