Download e-book for kindle: Architecture of Computing Systems – ARCS 2015: 28th by Luís Miguel Pinho Pinho, Wolfgang Karl, Albert Cohen, Uwe

By Luís Miguel Pinho Pinho, Wolfgang Karl, Albert Cohen, Uwe Brinkschulte

ISBN-10: 3319160850

ISBN-13: 9783319160856

ISBN-10: 3319160869

ISBN-13: 9783319160863

This publication constitutes the lawsuits of the twenty eighth foreign convention on structure of Computing structures, ARCS 2015, held in Porto, Portugal, in March 2015.

The 19 papers awarded including 3 invited papers have been conscientiously reviewed and chosen from forty five submissions. The papers are prepared in six periods protecting the subjects: undefined, layout, functions, belief and privateness, real-time matters and a top papers session.

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Additional info for Architecture of Computing Systems – ARCS 2015: 28th International Conference, Porto, Portugal, March 24-27, 2015, Proceedings

Sample text

Section 3). The challenge is that available embedded processor architectures do not offer spatial separation means for interrupts like an Input/Output Memory Management Unit (IOMMU) with sufficiently fine granularity (cf. Section 3 and [2]). Server or high-end workstation processor architectures providing such means (cf. Section 2 and [4] [5]) are not usable for embedded real-time systems because of size, weight, power, cooling, harsh environmental conditions, certification considerations, etc. Further constraints are the use of Commercial Off–The–Shelf (COTS) components.

The rest of the paper is organized as follows. Section 2 presents related work while Section 3 presents a motivational example. Section 4 describes the proposed methodology whose experimental results are presented in Section 5. Finally Section 6 presents the conclusions of the paper. 2 Related Work Synthesis of DoAll loops is a very well studied topic of High Level Synthesis so that many approaches have been proposed to address this problem. Identification of this type of loops can be performed by means of Polyhedral methodologies, which allow to analyze and transform source code specifications exposing the different possibilities of parallelizing a loop.

The area results refer only to the synthesized accelerator since the produced parallel hardware architectures, differently from the ones presented in [2], do not require any external processor nor external controller to be integrated in the system. Memory utilization has not been reported since all the benchmarks have been synthesized assuming that input and output data are stored in external memories. The results obtained on the different platforms are similar, so that the proposed methodology can actually be considered as appliable to different families of FPGAs.

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Architecture of Computing Systems – ARCS 2015: 28th International Conference, Porto, Portugal, March 24-27, 2015, Proceedings by Luís Miguel Pinho Pinho, Wolfgang Karl, Albert Cohen, Uwe Brinkschulte


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